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cy62167ev30 mobl ? 16-mbit (1m x 16 / 2m x 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05446 rev. *j revised june 29, 2011 168) static ram features tsop i package configurable as 1m 16 or 2m x 8 sram very high speed: 45 ns temperature ranges ? industrial: ?40 c to +85 c ? automotive-a: ?40 c to +85 c wide voltage range: 2.20 v to 3.60 v ultra-low standby power ? typical standby current: 1.5 ? a ? maximum standby current: 12 ? a ultra-low active power ? typical active current: 2.2 ma at f = 1 mhz easy memory expansion with ce 1 , ce 2 , and oe features automatic power-down when deselected cmos for optimum speed and power offered in pb-free 48-ball vfbga and 48-pin tsop i packages functional description the cy62167ev30 is a high performance cmos static ram organized as 1m words by 16 bits or 2m words by 8 bits. this device features an advanced circ uit design that provides an ultra low active current. ultra low active current is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that reduces power consumption by 99 percent when addresses are not toggling. place the device into standby mode when deselected (ce 1 high or ce 2 low or both bhe and ble are high). the input and output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when: the device is deselected (ce 1 high or ce 2 low), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or a write operation is in progress (ce 1 low, ce 2 high and we low). to write to the device, take chip enables (ce 1 low and ce 2 high) and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ) is written into the location spec ified on the address pins (a 0 through a 19 ). if byte high enable (bhe ) is low, then data from the i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 19 ). to read from the device, take chip enables (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appears on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see the ?truth table? on page 11 for a complete description of read and write modes. 1m 16 / 2m x 8 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 we ble bhe a 16 a 0 a 1 a 17 a 9 a 18 a 10 ce 2 ce 1 a 19 byte power down circuit bhe ble ce 2 ce 1 logic block diagram
cy62167ev30 mobl ? document #: 38-05446 rev. *j page 2 of 17 contents pin configuration ............................................................. 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 4 thermal resistance .......................................................... 5 data retention characteristics ....................................... 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definition ........................................... 12 package diagrams .......................................................... 13 acronyms ........................................................................ 15 document conventions ................................................. 15 units of measure ....................................................... 15 document history page ................................................. 16 sales, solutions, and legal information ...................... 17 worldwide sales and design s upport ......... .............. 17 products .................................................................... 17 psoc solutions ......................................................... 17
cy62167ev30 mobl ? document #: 38-05446 rev. *j page 3 of 17 pin configuration figure 1. 48-ball vfbga (6 x 8 x 1mm) top view [1, 2] figure 2. 48-pin tsop i top view [2, 3] product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( ? a) f = 1 mhz f = f max min typ [4] max typ [4] max typ [4] max typ [4] max cy62167ev30ll industrial/auto-a 2.2 3.0 3.6 45 2.2 4.0 25 30 1.5 12 we a 11 a 10 a 6 a 0 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe vss a 7 i/o 0 bhe ce 2 a 17 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 19 a 18 nc 3 2 6 5 4 1 d e b a c f g h a 16 nc v cc a 1 a 2 a 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 a19 nc we ce 2 nc bhe ble a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte vss i/o15/a20 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 vcc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 oe vss ce 1 a0 notes 1. ball h6 for the vfbga package can be used to upgrade to a 32m density. 2. nc pins are not connected on the die. 3. the byte pin in the 48-pin tsopi package has to be tied to v cc to use the device as a 1m x 16 sram. the 48-pin tsopi package can also be used as a 2m x 8 sram by tying the byte signal to v ss . in the 2m x 8 configuration, pin 45 is a20, while bhe , ble and i/o 8 to i/o 14 pins are not used. 4. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc (typ), t a = 25 c.
cy62167ev30 mobl ? document #: 38-05446 rev. *j page 4 of 17 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ............................... ?65 c to + 150 c ambient temperature with power applied .......................................... ?55 c to + 125 c supply voltage to ground potential ..............................?0.3 v to 3.9 v v cc (max) + 0.3 v dc voltage applied to outputs in high z state [5, 6] ..............?0.3 v to 3.9 v v cc (max) + 0.3 v dc input voltage [5, 6] ........ ?0.3 v to 3.9 v (v cc (max) + 0.3 v output current into outputs (low) ............................. 20 ma static discharge voltage........................................... >2001 v (mil-std-883, method 3015) latch-up current ...................................................... >200 ma operating range device range ambient temperature v cc [7] cy62167ev30ll industrial/ auto-a ?40 c to +85 c 2.2 v to 3.6 v electrical characteristics over the operating range parameter description test conditions 45 ns (industrial/auto-a) unit min typ [8] max v oh output high voltage 2.2 < v cc < 2.7 i oh = ?0.1 ma 2.0 ? ? v 2.7 < v cc < 3.6 i oh = ?1.0 ma 2.4 ? ? v v ol output low voltage 2.2 < v cc < 2.7 i ol = 0.1 ma ? ? 0.4 v 2.7 < v cc < 3.6 i ol = 2.1 ma ? ? 0.4 v v ih input high voltage 2.2 < v cc < 2.7 1.8 ? v cc + 0.3 v v 2.7 < v cc < 3.6 2.2 ? v cc + 0.3 v v v il input low voltage 2.2 < v cc < 2.7 ?0.3 ? 0.6 v 2.7 < v cc < 3.6 for vfbga package ?0.3 ? 0.8 v for tsop i package ?0.3 ? 0.7 [9] v i ix input leakage current gnd < v i < v cc ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc (max) i out = 0 ma cmos levels ?25 30ma f = 1 mhz ? 2.2 4.0 ma i sb1 [10] automatic power down current?cmos inputs ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2v, v in < 0.2 v) f = f max (address and data only), f = 0 (oe , and we ), v cc = v cc (max) ?1.5 12 ? a i sb2 [10] automatic power down current?cmos inputs ce1 > v cc ? 0.2v or ce2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v cc (max) ?1.5 12 ? a capacitance parameter [11] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf notes 5. v il (min) = ?2.0 v for pulse durations less than 20 ns. 6. v ih (max) = v cc + 0.75 v for pulse durations less than 20 ns. 7. full device ac operation assumes a 100 ? s ramp time from 0 to v cc (min) and 200 ? s wait time after v cc stabilization. 8. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc (typ), t a = 25 c. 9. under dc conditions the device meets a v il of 0.8 v. however, in dynamic conditions input low voltag e applied to the device must not be higher than 0.7 v. this is applicable to tsop i package only. 10. chip enables (ce 1 and ce 2 ), byte enables (bhe and ble ) and byte must be tied to cmos levels to meet the i sb1 /i sb2 / i ccdr spec. other inputs can be left floating 11. tested initially and after any design or proc ess changes that may affect these parameters.
cy62167ev30 mobl ? document #: 38-05446 rev. *j page 5 of 17 thermal resistance parameter [12] description test conditions vfbga (6 x 8 x 1mm) tsop i unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 55 60 ? c/w ? jc thermal resistance (junction to case) 16 4.3 ? c/w figure 3. ac test loads and waveforms parameters 2.2 v to 2.7 v 2.7 v to 3.6 v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thvenin equivalent all input pulses r th r1 note 12. tested initially and after any design or proc ess changes that may affect these parameters.
cy62167ev30 mobl ? document #: 38-05446 rev. *j page 6 of 17 data retention characteristics over the operating range parameter description conditions min typ [13] max unit v dr v cc for data retention 1.5 ? ? v i ccdr [14] data retention current v cc = 1.5 v to 3.0 v, ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v industrial 48-pin tsop i ??8 ? a v cc = 1.5 v, ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v industrial other packages ??10 ? a auto-a all packages ? ? 10 ? a t cdr [15] chip deselect to data retention time 0??? t r [16] operation recovery time 45 ? ? ns figure 4. data retention waveform notes 13. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc (typ), t a = 25 c. 14. chip enables (ce 1 and ce 2 ), byte enables (bhe and ble ) and byte must be tied to cmos levels to meet the i sb1 /i sb2 / i ccdr spec. other inputs can be left floating 15. tested initially and after any design or proc ess changes that may affect these parameters. 16. full device operation requires linear v cc ramp from v dr to v cc (min) > 100 ? s or stable at v cc (min) > 100 ? s. 17. bhe .ble is the and of both bhe and ble . deselect the chip by either disabling the chip enable signals or by disabling both bhe and ble . v cc (min) v cc (min) t cdr v dr > 1.5 v data retention mode t r ce 1 or v cc bhe . ble ce 2 or [17]
cy62167ev30 mobl ? document #: 38-05446 rev. *j page 7 of 17 switching characteristics parameter [18, 19] description 45 ns (industrial/auto-a) unit min max read cycle t rc read cycle time 45 ? ns t aa address to data valid ? 45 ns t oha data hold from address change 10 ? ns t ace ce 1 low and ce 2 high to data valid ? 45 ns t doe oe low to data valid ? 22 ns t lzoe oe low to low z [20] 5?ns t hzoe oe high to high z [20, 21] ?18ns t lzce ce 1 low and ce 2 high to low z [20] 10 ? ns t hzce ce 1 high and ce 2 low to high z [20, 21] ?18ns t pu ce 1 low and ce 2 high to power-up 0 ? ns t pd ce 1 high and ce 2 low to power-down ? 45 ns t dbe ble / bhe low to data valid ? 45 ns t lzbe ble / bhe low to low z [20] 10 ? ns t hzbe ble / bhe high to high z [20, 21] ?18ns write cycle [22] t wc write cycle time 45 ? ns t sce ce 1 low and ce 2 high to write end 35 ? ns t aw address setup to write end 35 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 35 ? ns t bw ble / bhe low to write end 35 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [20, 21] ?18ns t lzwe we high to low z [20] 10 ? ns notes 18. test conditions for all parameters other than tri-state parame ters assume signal transition time of 1 v/ns, timing reference levels of v cc (typ)/2, input pulse levels of 0 to v cc (typ), and output loading of the specified i ol /i oh as shown in ?ac test loads and waveforms? on page 5. 19. ac timing parameters are subject to byte enable signals (bhe or ble ) not switching when chip is disabled. see application note an13842 for further clarification. 20. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 21. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedance state. 22. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe or ble or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going in active. the data input setup and hold timing must refer to the edge of the signal that terminates the write.
cy62167ev30 mobl ? document #: 38-05446 rev. *j page 8 of 17 switching waveforms figure 5. read cycle no. 1 (a ddress transition controlled) [23, 24] figure 6. read cycle no. 2 (oe controlled) [24, 25] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzbe t lzbe t hzce t dbe oe ce 1 address ce 2 bhe /ble data out v cc supply current high i cc i sb impedance notes 23. the device is continuously selected. oe , ce 1 = v il , bhe , ble or both = v il , and ce 2 = v ih . 24. we is high for read cycle. 25. address valid before or similar to ce 1 , bhe , ble transition low and ce 2 transition high.
cy62167ev30 mobl ? document #: 38-05446 rev. *j page 9 of 17 figure 7. write cycle no. 1 (we controlled) [26, 27, 28] figure 8. write cycle no. 2 (ce 1 or ce 2 controlled) [26, 28] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data t bw note 29 ce 1 address ce 2 we data i/o oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data t bw t sa note 29 ce 1 address ce 2 we data i/o oe bhe /ble notes 26. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe or ble or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must refer to the edge of the signal that terminates the write 27. data i/o is high impedance if oe = v ih . 28. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 29. during this period the i/os are in output state. do not apply input signals.
cy62167ev30 mobl ? document #: 38-05446 rev. *j page 10 of 17 figure 9. write cycle no. 3 (we controlled, oe low) [30] figure 10. write cycle no. 4 (bhe /ble controlled, oe low) [30] switching waveforms (continued) valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 31 ce 1 address ce 2 we data i/o bhe /ble t hd t sd t sa t ha t aw t wc valid data t bw t sce t pwe note 31 ce 1 address ce 2 we data i/o bhe /ble notes 30. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 31. during this period the i/os are in output state. do not apply input signals.
cy62167ev30 mobl ? document #: 38-05446 rev. *j page 11 of 17 truth table ce 1 ce 2 we oe bhe ble inputs/outputs mode power hx [32] xxx [32] x [32] high z deselect/power-down standby (i sb ) x [32] lxxx [32] x [32] high z deselect/power-down standby (i sb ) x [32] x [32] x x h h high z deselect/power-down standby (i sb ) l h h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) l h h l h l data out (i/o 0 ?i/o 7 ); high z (i/o 8 ?i/o 15 ) read active (i cc ) lhhllhhigh z (i/o 0 ?i/o 7 ); data out (i/o 8 ?i/o 15 ) read active (i cc ) l h h h l h high z output disabled active (i cc ) lhhhhlhigh z output disabled active (i cc ) l h h h l l high z output disabled active (i cc ) l h l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l h l x h l data in (i/o 0 ?i/o 7 ); high z (i/o 8 ?i/o 15 ) write active (i cc ) lhlxlhhigh z (i/o 0 ?i/o 7 ); data in (i/o 8 ?i/o 15 ) write active (i cc ) note 32. the ?x? (don?t care) state for the chip enables and byte enables in the truth table refer to the logic state (either high or low). intermediate voltage levels on these pins is not permitted.
cy62167ev30 mobl ? document #: 38-05446 rev. *j page 12 of 17 ordering code definition ordering information speed (ns) ordering code package diagram package type operating range 45 cy62167ev30ll-45bvi 51-85150 48-ball vfbga (6 8 1 mm) industrial cy62167ev30ll-45bvxi 51 -85150 48-ball vfbga (6 8 1 mm) (pb-free) cy62167ev30ll-45zxi 51-85183 48-pin tsop i (pb-free) CY62167EV30LL-45BVXA 51-85150 48-ball vfbga (6 8 1 mm) (pb-free) automotive-a cy62167ev30ll-45zxa 51-85183 48-pin tsop i (pb-free) cy 621 = mobl sram family 621 6 7 density = 16 mbit company id: cy = cypress e bus width = x16 e = process technology 90 nm v30 voltage range = 3 v typical ll low power 45 speed grade xxx package type: bvx: vfbga (pb-free) zsx: tsop ii (pb-free) x temperature grades: i = industrial a = auto-a
cy62167ev30 mobl ? document #: 38-05446 rev. *j page 13 of 17 package diagrams figure 11. 48-ball vfbga (6 x 8 x 1 mm), 51-85150 51-85150-*e
cy62167ev30 mobl ? document #: 38-05446 rev. *j page 14 of 17 figure 12. 48-pin tsop i (12 mm 18.4 mm 1.0 mm), 51-85183 51-85183 *c
cy62167ev30 mobl ? document #: 38-05446 rev. *j page 15 of 17 acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tsop thin small outline package vfbga very fine ball grid array we write enable symbol unit of measure c degrees celsius ? a microamperes ma milliamperes mhz megahertz ns nanoseconds pf picofarads v volts ? ohms w watts
cy62167ev30 mobl ? document #: 38-05446 rev. *j page 16 of 17 document history page document title: cy62167ev30 mobl ? 16-mbit (1m x 16 / 2m x 8) static ram document number: 38-05446 rev. ecn no. orig. of change submission date description of change ** 202600 aju 01/23/2004 new data sheet *a 463674 nxr see ecn converted from ad vance information to preliminary removed ?l? bin and 35 ns speed bin from product offering modified data sheet to include x8 configurability. changed ball e3 in fbga pinout from dnu to nc changed the i sb2(typ) value from 1.3 ? a ? to ? 1.5 ? a changed the i cc(max) value from 40 ma to 25 ma changed vcc stabilization time in footnote #9 from 100 s to 200 s changed the ac test load capacitance value from 50 pf to 30 pf corrected typo in data retention characteristics (t r ) from 100 s to t rc ns changed t oha , t lzce , t lzbe , and t lzwe from 6 ns to 10 ns changed t lzoe from 3 ns to 5 ns. changed t hzoe , t hzce , t hzbe , and t hzwe from 15 ns to 18 ns changed t sce , t aw , and t bw from 40 ns to 35 ns changed t pe from 30 ns to 35 ns changed t sd from 20 ns to 25 ns updated 48 ball fbga package information. updated the ordering information table *b 469169 nsi see ecn minor change: moved to external web *c 1130323 vkn see ecn converted from preliminary to final changed i cc max spec from 2.8 ma to 4.0 ma for f = 1mhz changed i cc typ spec from 22 ma to 25 ma for f = f max changed i cc max spec from 25 ma to 30 ma for f = f max added v il spec for tsop i package and footnote# 9 added footnote# 10 related to i sb2 and i ccdr changed i sb1 and i sb2 spec from 8.5 ? a to 12 ? a changed i ccdr spec from 8 ? a to 10 ? a added footnote# 15 related to ac timing parameters *d 1323984 vkn/aesa see ecn modified i ccdr spec for tsop i package added 48-ball vfbga (6 x 7 x 1mm) package added footnote# 1 related to vfbga (6 x 7 x 1mm) package updated ordering information table *e 2678799 vkn/pyrs 03/25/2009 added automotive-a information *f 2720234 vkn/aesa 06/17/2009 included -45bvxa pa rt in the ordering information table *g 2880574 vkn 02/18/2010 modified i ccdr spec from 8 ? a to 10 ? a for auto-a grade. added contents . updated all package diagrams. updated links in sales, solutions, and legal information. *h 2934396 vkn 06/03/10 added footnote #25 related to chip enable. updated template. *i 3006301 rame 08/12/2010 included bhe and ble in i sb1 , i sb2 , and i ccdr test conditions to reflect byte power down feature. removed 48-ball vfbga (6 x 7 x 1 mm) package related information. added acronyms and ordering code definition. format updates to match template. *j 3295175 rame 06/29/2011 updated package diagrams . added document conventions . removed reference to an10 64 sram system guidelines. added i sb1 to footnotes 10 and 14. added byte enables to footnote 32 and referenced to truth table. updated table of contents.
document #: 38-05446 rev. *j revised june 29, 2011 page 17 of 17 mobl is a registered trademark, and more battery life is a trademark, of cypress semiconductor. all products and company names mentioned in this document may be the trademarks of their respective holders. cy62167ev30 mobl ? ? cypress semiconductor corporation, 2004-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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